In recent years, components such as CPUs, which configure an information processing system such as a server or a computer, each has achieved an increase in performance, and in particular, bandwidths have been greatly improved. In order to increase the total bandwidth of the entire information processing system, communication circuits to perform data communication between components such as CPUs have to be speeded up. In a communication circuit that performs high-speed data communication, an equalizer to compensate the deterioration of a data signal, which occurs in a communication channel, is used.
As one of examples of the equalizer, there is a decision feedback equalizer (DFE) (see, for example, Sam Palermo, “ECEN720: High-Speed Links Circuits and Systems Spring 2013”). As an example illustrated in FIG. 16, the decision feedback equalizer includes an adder 1601, a comparator 1602, and a feedback filter 1603. In accordance with a determination result of the comparator 1602, the decision feedback equalizer changes a determination threshold of the comparator 1602 by an amount corresponding to the magnitude of inter symbol interference (ISI) that may occur in the communication circuit.
In the decision feedback equalizer, every time the comparator 1602 determines an input signal, the feedback filter 1603 obtains a weighted sum, based on a determination result (dk) of the comparator 1602 and coefficient W1, . . . , Wn-1, and Wn set from the outside, and the adder 1601 adds the obtained weighted sum to a reception signal yk as an offset voltage of the comparator 1602. In addition, the comparator 1602 performs determination while defining an output zk of the adder 1601 as an input signal, thereby outputting a determination result as a reception data signal. In this way, the decision feedback equalizer changes the determination threshold of the comparator by an amount of the inter symbol interference. Therefore, it becomes possible to compensate the deterioration of the data signal, caused by the inter symbol interference.
Here, in general, from a viewpoint of power consumption, a comparator that has a reset period for performing a reset operation and an evaluation period for performing a determination operation (a comparison operation) is used as the comparator used for decision feedback equalizer. In a case where the comparator used for the decision feedback equalizer performs the reset operation, a time-interleaved configuration in which comparators are parallelized is used. However, the reset operation performed by the comparator results in disappearance of a determination result output by the comparator. Therefore, in order to avoid a situation that the reset operation results in the disappearance of the determination result of the comparator, thereby causing no previous determination result to be reflected in a comparator that currently performs a determination operation, there is proposed a technology for adding, to a subsequent stage of the comparator, a latch circuit to hold a determination result (see, for example, R. Payne et al., “A 6.25-Gb/s Binary Transceiver in 0.13-um CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels”, IEEE 1 Solid-State Circuits, vol. 40, no. 12, pp. 2646-2657, December 2005).